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cmos-ccd 1h delay line for ntsc description the cxl5502m/n/p are cmos-ccd delay line ics that provide 1h delay time for ntsc signals including the external low-pass filter. the ics contain a pll circuit (quadruple progression). features single power supply (5v) low power consumption 95mw (typ.) built-in peripheral circuits clamp level of i/o signal can be selected built-in quadruple pll circuit functions 905-bit ccd register clock driver autobias circuit input clamp circuit sample and hold circuit pll circuit (quadruple progression) structure cmos-ccd absolute maximum ratings (ta = 25?) supply voltage v dd 6v operating temperature topr ?0 to +60 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d cxl5502m 400 mw cxl5502n 260 mw cxl5502p 800 mw recommended operating condition (ta = 25?) supply voltage v dd 5 5% v recommended clock conditions (ta = 25?) input clock amplitude v clk 0.3 to 1.0 vp-p (0.5vp-p typ.) clock frequency f clk 3.579545 mhz input clock waveform sine wave input signal amplitude v sig 500mvp-p (typ.), 572mvp-p (max.) (at internal clamp condition) ?1 e89930e79-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxl5502m/n/p cxl5502m 14 pin sop (plastic) cxl5502n 16 pin ssop (plastic) cxl5502p 14 pin dip (plastic)
? 2 cxl5502m/n/p a u t o b i a s c i r c u i t c l o c k d r i v e r b i a s c i r c u i t ( a ) b i a s c i r c u i t ( b ) p l l t i m i n g c i r c u i t c c d ( 9 0 5 b i t ) c l a m p c i r c u i t o u t p u t c i r c u i t ( s / h 1 b i t ) a a 1 4 v s s 1 2 v d d 1 1 v c o i n 1 0 p c o u t 9 v d d 8 c l k 1 i n 2 i / o 1 3 i / o 2 4 o u t 5 v s s 7 v c o o u t 6 v s s i / o c o n t r o l 1 3 a b a a 1 4 v d d 1 2 p c o u t 1 1 ( n . c ) 1 0 v d d 9 c l k 8 v c o o u t 1 i n 2 i / o 1 3 i / o 2 4 o u t 5 v s s 7 v s s 6 ( n . c ) 1 3 v c o o u t 1 5 a b 1 6 v s s b l o c k d i a g r a m a n d p i n c o n f i g u r a t i o n ( t o p v i e w ) c x l 5 5 0 2 m / p c x l 5 5 0 2 n a u t o b i a s c i r c u i t c l o c k d r i v e r b i a s c i r c u i t ( a ) b i a s c i r c u i t ( b ) p l l t i m i n g c i r c u i t c c d ( 9 0 5 b i t ) c l a m p c i r c u i t o u t p u t c i r c u i t ( s / h 1 b i t ) i / o c o n t r o l
? 3 cxl5502m/n/p pin description cxl5502m/p cxl5502n pin no. symbol i/o description impedance 1 2 3 4 5 6 7 8 9 10 11 12 13 14 in i/o1 i/o2 out v ss v ss vco out clk v dd pc out vco in v dd ab v ss i i i o o i o i o signal input i/o control 1 i/o control 2 signal output gnd gnd vco output clock input power supply (5v) phase comparator output vco input power supply (5v) autobias dc output gnd (sub) > 10k at no clamp 40 to 500 > 100k 600 to 200k pin no. symbol i/o description impedance 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 in i/o1 i/o2 out v ss (n.c) v ss vco out clk v dd (n.c) pc out vco in v dd ab v ss i i i o o i o i o signal input i/o contorl 1 i/o contorl 2 signal output gnd gnd vco output clock input power supply (5v) phase comparator output vco input power supply (5v) autobias dc output gnd (sub) > 10k at no clamp 40 to 500 > 100k 600 to 200k
? 4 cxl5502m/n/p description of function in the cxl5502m/n/p, the condition of i/o control pins (pins 2 and 3) control the input signal clamp condition and the mode of the output signal with relation to its input signal. there are 2 modes for the i/o signal. (1) pn mode (low level clamp/reverse phase output mode) (2) np mode (high level clamp/positive phase output mode) i/o control pin (1) i/o1 (pin 2) control of the i/o signal condition dc open ..... input signal is low level clamped and the output signal is inverted in relation to the input signal. as the pin is biased to 2.5v by means of the resistance inside the ic, a decoupling capacitor of around 1000pf is necessary. gnd ............. input signal is high level clamped and the output signal turns into an inverted signal. (2) i/o2 (pin 3) control of the input signal clamp condition 0v ................. internal clamp condition 5v ................. non internal clamp condition center biased to approx. 2.1v by means of the ic internal resistance (several 10k ). usage in this mode is limited to apl 50% signals and in this mode, the maximum input signal amplitude is 200mvp-p. c l a m p l e v e l i n p u t w a v e f o r m o u t p u t w a v e f o r m c l a m p l e v e l
? 5 cxl5502m/n/p 2.1 vinpn + 0.5 vinnp b a b a b a b a b a b a b a b a b a b a b a b a b a b a 10 ? ? 0 0 52 19 0 ? 5 5 56 28 2 0 7 7 350 ma db db % degree mvp-p db 2 3 4 5 5 6 7 unit note max. min. typ. bias condition vbias1 (v) (note 1) electrical characteristics (ta = 25 c, v dd = 5v, f clk = 3.579545mhz, v clk = 500mvp-p, sine wave) see "electrical characteristics test circuit" notes (1) vinpn and vinnp are defined as follows. vinpn and vinnp are the input signal clamp levels of pn and np modes clamping the video signal sync tip level. testing of vinpn and vinnp is executed with a voltmeter under the following sw conditions. item symbol test condition sw condition 1 2 3 4 5 6 7 a b c d d e c a a a b a b c a b b b a b b a b a a b a a b a b b c c a d 200khz, 500mvp-p, sine wave 200khz ? ? 3.57mhz, 150mvp-p, sine wave 5-staircase wave (see note 5) 5-staircase wave (see note 5) no signal input 50% white video signal (see note 7) iddpn iddnp glpn glnp fpn fnp dgpn dgnp dppn dpnp cppn cpnp snpn snnp supply current low frequency gain frequency response differential gain differential phase s/h pulse coupling s/n ratio ? ? 1 i n p u t ( i n ) v i n p n c x l 5 5 0 2 v i n n p sw condition item vinpn vinnp test point v1 1 2 c c 3 b b 4 b a 5 b a 6 a a 7
? 6 cxl5502m/n/p (2) this is the ic supply current value during clock and signal input. (3) glpn, glnp are output gain of out pin when a 500mvp-p, 200khz sine wave is fed to in pin. (example of calculation) glpn = 20 log [db] (4) indicates the dissipation at 3.57mhz in relation to 200khz. from the output voltage at out pin when a 150mvp-p, 200khz sine wave is fed to in pin, and from the output voltage at out pin when a 150mvp-p, 3.57mhz sine wave is fed to same, calculation is made according to the following formula. the input part bias is tested at 2.1v. (example of calculation) fpn = 20 log [db] (5) the differential gain (dg) and the differential phase (dp), when the 5-staircase wave in the figure below is input are tested at the vector scope. input waveform (input waveform of np mode is the inverted waveform in the figure above) (6) the internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. the input part bias is tested at vinpn + 0.5v and vinnp for pn and np modes respectively. out pin output voltage (pn mode) [mvp-p] 500 [mvp-p] out pin otuput voltage (pn mode, 3.57mhz) [mvp-p] out pin output voltage (pn mode, 200khz) [mvp-p] 1 h 6 3 . 5 6 s 1 4 3 m v 3 5 7 m v 5 0 0 m v 1 4 3 m v t e s t v a l u e ( m v p - p )
? 7 cxl5502m/n/p (7) s/n ratio during a 50% white video signal input shown in figure below is tested at a video noise meter, in bpf 100khz to 4mhz, sub carrier trap mode. input waveform (input waveform of np mode is the inverted waveform in the figure above) clock 1 h 6 3 . 5 6 s 1 4 3 m v 1 7 8 m v 3 2 1 m v 0 . 3 v p - p t o 1 . 0 v p - p ( 0 . 5 v p - p t y p . ) f s c ( 3 . 5 7 9 5 4 5 m h z ) s i n e w a v e
? 8 cxl5502m/n/p electrical characteristics test circuit (using cxl5502m/p) v s s a b v d d v c o i n p c o u t v d d c l k 1 0 0 0 p 1 0 0 0 p 3 . 3 3 . 3 0 . 1 1 k 8 2 k 0 . 1 1 c l k f s c ( 3 . 5 7 9 5 4 5 m h z ) 0 . 5 v p - p s i n e w a v e i n i / o 1 i / o 2 o u t v s s v c o o u t v s s a b s w 6 a b 1 m 1 k a v 1 5 v c 1 0 0 0 p 1 s w 2 b s w 1 c 2 0 0 k h z 5 0 0 m v p - p s i n e w a v e 2 0 0 k h z 1 5 0 m v p - p s i n e w a v e 3 . 5 7 m h z 1 5 0 m v p - p s i n e w a v e 5 - s t a i r c a s e w a v e 5 0 % w h i t e v i d e o s i g n a l a b d e a s w 7 2 . 1 k 9 v 2 3 4 5 6 7 1 b c d o s c i l l o s c o p e s p e c t r u m a n a l y z e r v e c t o r s c o p e n o i s e m e t e r n o t e 1 ) n o t e 2 ) 3 3 l p f b p f n o t e 1 ) l p f f r e q u e n c y r e s p o n s e 0 3 5 0 6 m 1 4 . 3 m [ h z ] f r e q u e n c y [ d b ] n o t e 2 ) b p f f r e q u e n c y r e s p o n s e 0 3 5 0 6 m 1 4 . 3 m [ h z ] f r e q u e n c y [ d b ] 2 0 0 8 9 1 0 1 1 1 2 1 3 1 4 s w 3 v b i a s 1 c x l 5 5 0 2 m / p a 1 1 1 0 0 0 p a b a b s w 4 s w 5 * when using cxl5502n, change the connection terminal only. (see the block diagram and pin configuration. for nc pins, ground them.)
? 9 cxl5502m/n/p application circuit (using cxl5502m/p) 1 0 0 0 p 3 . 3 1 k 3 . 3 0 . 1 8 2 k 1 0 0 0 p 0 . 1 1 f s c 0 . 5 v p - p s i n e w a v e 1 m 1 3 3 p 3 3 0 k 8 9 1 0 1 1 1 2 1 3 1 4 5 v 2 3 4 5 6 7 1 i n p u t 4 7 0 2 7 0 0 5 6 0 k 1 k l p f 2 7 p 2 2 0 0 2 2 0 0 5 v 2 2 0 0 1 o u t p u t t r a n s i s t o r u s e d p n p : 2 s a 1 1 7 5 t r a n s i s t o r u s e d n p n : 2 s c 4 0 3 d e l a y t i m e 2 5 0 n s ( e x . t h 3 5 6 l s m - 4 3 0 3 z e d t o u k o u m a d e ) a a ( p o s i t i v e p h a s e s i g n a l ) a ( p o s i t i v e p h a s e s i g n a l ) a a ( r e v e r s e p h a s e s i g n a l ) 1 0 0 0 p 7 1 . 8 k 4 f s c 2 s c 4 0 3 1 . 8 k 5 v v c o o u t ( p i n 7 ) i n u s e c x l 5 5 0 2 m / p * when using cxl5502n, change the connection terminal only. (see the block diagram and pin configuration. for nc pins, ground them.) application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 10 cxl5502m/n/p e x a m p l e o f r e p r e s e n t a t i v e c h a r a c t e r i s t i c s l o w f r e q u e n c y g a i n v s . a m b i e n t t e m p e r a t u r e 2 0 0 2 0 4 0 6 0 8 0 3 2 1 0 1 a m b i e n t t e m p e r a t u r e [ c ] l o w f r e q u e n c y g a i n [ d b ] d i f f e r e n t i a l g a i n v s . a m b i e n t t e m p e r a t u r e 2 0 0 2 0 4 0 6 0 8 0 2 4 6 8 1 0 0 a m b i e n t t e m p e r a t u r e [ c ] d i f f e r e n t i a l g a i n [ % ] l o w f r e q u e n c y g a i n v s . s u p p l y v o l t a g e 4 . 7 5 5 5 . 2 5 3 2 1 0 1 s u p p l y v o l t a g e [ v ] l o w f r e q u e n c y g a i n [ d b ] s u p p l y c u r r e n t v s . a m b i e n t t e m p e r a t u r e 2 0 0 2 0 4 0 6 0 8 0 1 0 3 0 2 0 a m b i e n t t e m p e r a t u r e [ c ] s u p p l y c u r r e n t [ m a ] f r e q u e n c y r e s p o n s e v s . a m b i e n t t e m p e r a t u r e 2 0 0 2 0 4 0 6 0 8 0 2 1 0 3 a m b i e n t t e m p e r a t u r e [ c ] f r e q u e n c y r e s p o n s e [ d b ] s u p p l y c u r r e n t v s . s u p p l y v o l t a g e 4 . 7 5 5 5 . 2 5 1 0 3 0 2 0 s u p p l y v o l t a g e [ v ] s u p p l y c u r r e n t [ m a ]
? 11 cxl5502m/n/p d i f f e r e n t i a l g a i n v s . s u p p l y v o l t a g e 4 . 7 5 5 5 . 2 5 2 4 6 8 1 0 0 s u p p l y v o l t a g e [ v ] d i f f e r e n t i a l g a i n [ % ] f r e q u e n c y r e s p o n s e v s . s u p p l y v o l t a g e 4 . 7 5 5 5 . 2 5 2 1 0 3 s u p p l y v o l t a g e [ v ] f r e q u e n c y r e s p o n s e [ d b ] f r e q u e n c y r e s p o n s e 1 0 k 1 0 0 k 1 m 6 4 2 0 2 f r e q u e n c y [ h z ] g a i n [ d b ] 1 0 m
? 12 cxl5502m/n/p package outline unit: mm cxl5502m 1 4 p i n s o p ( p l a s t i c ) 9 . 9 0 . 1 + 0 . 4 0 . 4 5 0 . 1 1 . 2 7 7 . 9 0 . 4 5 . 3 0 . 1 + 0 . 3 6 . 9 0 . 5 0 . 2 0 . 2 0 . 0 5 + 0 . 1 0 . 1 0 . 0 5 + 0 . 2 1 . 8 5 0 . 1 5 + 0 . 4 m 0 . 2 4 s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 / c o p p e r a l l o y s o p - 1 4 p - l 0 1 s o p 0 1 4 - p - 0 3 0 0 0 . 2 g 1 7 1 4 8 0 . 1 5 1 4 p i n s o p ( p l a s t i c ) 3 0 0 m i l 2 0 m a x 1 . 2 7 5 . 3 0 . 3 1 0 . 2 0 . 3 0 . 1 5 0 . 1 5 0 . 0 5 1 0 m a x s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e w e i g h t e p o x y r e s i n s o l d e r p l a t i n g c o p p e r / 4 2 a l l o y s o p - 1 4 p - l 1 2 1 * s o p 0 1 4 - p - 0 3 0 0 - a x 1 4 8 0 . 4 0 . 1 1 . 4 4 m a x 7 . 8 0 . 4 1 7 a 0 . 7 5 0 . 2 0 . 0 5 m i n d e t a i l a m 0 . 1 3 0 . 2 g
? 13 cxl5502m/n/p 1 6 p i n s s o p ( p l a s t i c ) s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r / p a l l a d i u m 4 2 / c o p p e r a l l o y 0 . 1 g s s o p - 1 6 p - l 0 1 s s o p 0 1 6 - p - 0 0 4 4 * 5 . 0 0 . 1 0 . 6 5 0 . 2 2 0 . 0 5 + 0 . 1 8 1 9 1 6 * 4 . 4 0 . 1 6 . 4 0 . 2 0 . 1 0 . 1 0 . 5 0 . 2 0 t o 1 0 0 . 1 5 0 . 0 2 + 0 . 0 5 1 . 2 5 0 . 1 + 0 . 2 a d e t a i l a 0 . 1 p l a t i n g n o t e : d i m e n s i o n * d o e s n o t i n c l u d e m o l d p r o t r u s i o n . 0 . 1 3 m 1 4 p i n d i p ( p l a s t i c ) 1 9 . 2 0 . 1 + 0 . 4 1 2 . 5 4 7 8 1 4 6 . 4 0 . 1 + 0 . 3 0 . 2 5 0 . 0 5 + 0 . 1 7 . 6 2 0 t o 1 5 3 . 7 0 . 1 + 0 . 4 0 . 5 m i n 0 . 5 0 . 1 3 . 0 m i n 1 . 2 0 . 1 5 s o n y c o d e e i a j c o d e j e d e c c o d e d i p - 1 4 p - 0 1 d i p 0 1 4 - p - 0 3 0 0 s i m i l a r t o m o - 0 0 1 - a h p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 / c o p p e r a l l o y 0 . 9 g cxl5502p cxl5502n

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